This application claims the benefit of Korean Patent Application No. 2001-9325, filed on Feb. 23, 2001, the contents of which are hereby incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a split-gate flash memory and a method of manufacturing the same.
2. Description of Related Art
Recently split-gate flash memories have found wide use as data storage elements.
FIG. 1 is a top plan view illustrating a structure of a conventional split-gate flash memory. FIGS. 2A to 2J are cross-sectional views taken along line A-Axe2x80x2 of FIG. 1, and FIGS. 3A to 3J are cross-sectional views taken along line B-Bxe2x80x2 of FIG. 1.
A method of manufacturing the conventional split-gate flash memory is now explained in detail with reference to FIGS. 1, 2A to 2J and 3A to 3J. Referring to FIGS. 2A and 3A, a first oxidation film 101 is formed on an active region of a semiconductor substrate 100. A first conductive layer 102 is provided on the first oxidation film 101 to form a field oxidation film 103 on a field region of the semiconductor substrate 100. Preferably, the field oxidation film 103 comprises polycrystalline silicon. The field oxidation film 103 may be formed, for example, using a local oxidation of silicon (LOCOS) process, a poly-buffered local oxidation of silicon (PBL) process, or a shallow-trench isolation (STI) process. The field oxidation film 103 of FIG. 3A is formed by the STI process.
In greater detail, the first oxidation film 101 and the first conductive layer 102 are sequentially deposited on the entire surface of the semiconductor substrate 100. A first nitride layer (not shown) is deposited on the first conductive layer 102. The first oxidation film 101, the first conductive layer 102 and the first nitride layer are patterned through a photolithography process to expose a portion of the semiconductor substrate corresponding to the field region. The exposed portion of the semiconductor substrate 100 is etched to form a trench (not shown). Thereafter, an oxidation film is deposited on the first nitride layer comprising the trench, and then a chemical-mechanical polish (CMP) process is performed until the first nitride layer is exposed. The oxidation film is then filled in the trench to form the field oxidation film 103. The first nitride layer remaining on the first conductive layer 102 is removed. After forming the field oxidation film 103, a second nitride layer 104 is deposited on the first conductive layer 102 and is patterned to expose a portion of the first conductive layer 102.
Referring to FIGS. 2B and 3B, a second oxidation film 105 is deposited over the whole surface of the semiconductor substrate 100 and covers the second nitride layer 104 and the exposed surface of the first conductive layer 102. Even though not shown, before depositing the second oxidation film 105, the first conductive layer 102 is etched using the second nitride layer 104 as a mask, or the exposed portion of the first conductive layer 102 is oxidized by an oxidation process, so that the exposed portion of the first conductive layer 102 is relatively thinner than the non-exposed portion thereof.
As shown in FIGS. 2C and 3C, the second oxidation film 105 is etched back to form an oxidation spacer 106 on a side wall of the second nitride layer 104. Then, using the oxidation spacer 106 as a mask, the exposed portions of the first oxidation film 101 and the first conductive layer 102, that are not covered with the oxidation spacer 106 and the second nitride layer 104, are etched to expose a corresponding portion of the semiconductor substrate 100. Using the oxidation spacer 106 and the second nitride layer 104 as a mask, impurities having a reverse conductivity to that of the semiconductor substrate 100 are ion-implanted into the exposed portion of the semiconductor substrate 100 to form a source junction region 107.
At this point, even though not shown, a side portion of the first conductive layer 102 is exposed while the first oxidation film 101 and the first conductive layer 102 are etched using the spacer 106 as a mask. In order to prevent a short circuit between the exposed side portion of the first conductive layer 102 and a source line that will be formed in a subsequent process, an oxidation film is deposited over the whole surface of the semiconductor substrate 100 by a chemical vapor deposition (CVD) technique and then is etched back to finally form the oxidation spacer 106 having a structure that surrounds the first conductive layer 102 as shown in FIG. 2C. Instead of the CVD process, a thermal oxidization process may be used to form the oxidation film.
Subsequently, as shown in FIGS. 2D and 3D, a second conductive layer is deposited over the whole surface of the semiconductor substrate 100 and is etched back to form the source line 109 that directly contacts the source junction region 107. At this point, the source line 109 is insulated from the first conductive layer 102 by the oxidation spacer 106.
As shown in FIGS. 2E and 3E, the second nitride layer 104 is selectively removed using, e.g., a phosphoric acid, and then the first oxidation film 101 and the first conductive layer 102 are etched using the oxidation spacer 106 as a mask to form a first gate insulating layer 110 and a floating gate 111.
As shown in FIGS. 2F and 3F, a third oxidation film 113 and a third conductive layer 114 are sequentially deposited over the whole surface of the semiconductor substrate 100. Preferably, the third conductive layer 114 is made of polycrystalline silicon. Thereafter, as shown in FIGS. 2G and 3G, the third oxidation film 113 and the third conductive layer 114 are simultaneously etched back to form a second gate insulating layer 115 and the word line 116 on a side wall of the oxidation spacer 106.
Subsequently, as shown FIGS. 2H and 3H, a fourth oxidation film and a third nitride layer are deposited over the whole surface of the semiconductor substrate 100 and then are etched back to form a buffer layer 117 and a spacer 118 on a side wall of the word line 116 and to expose a portion of the semiconductor substrate 100 corresponding to a drain junction region that will be formed in a subsequent process. Preferably, the spacer 118 comprises nitride.
As shown in FIGS. 2I and 3I, impurities having the same conductivity as that of the source junction region are ion-implanted into the exposed portion of the semiconductor substrate 100 using a mask (not shown) for an ion implantation to form the drain junction region 119.
Subsequently, as shown in FIGS. 2J and 3J, silicide layers 120 are formed on the source line 109, the drain junction region 119 and the word line 116 through a silicidation process. An interlayer insulator 121 is formed over the whole surface of the semiconductor substrate 100 and a contact hole 122 is formed to expose the drain region 119. The interlayer insulator 121 includes a contact hole 122 formed at a portion of the drain junction region 119. Finally, a metal line 123 is formed on the interlayer insulator 121 to contact the drain junction region 119 through the contract hole 122. Therefore, the conventional split-gate flash memory is completed.
A programming operation and an erasing operation of the conventional split-gate flash memory are explained below.
First, a programming operation of the conventional split-gate flash memory is as follows. As shown in FIG. 4A, a high voltage VDD is applied to the source junction region 107 through the source line 109, and a low voltage 0V is applied to the drain junction region 119. Electrons generated from the drain junction region 119 move toward the source junction region 107 through a channel region that is weakly inverted by a threshold voltage Vth applied to the word line 116. The electrons moving toward the source junction region 107 are excited due to a potential difference between the drain junction region 119 and the floating gate 111 in which a capacitance coupling occurs as a result of the high voltage applied to the source line 109 and then are injected into the floating gate 111. That is, a programming operation is performed by hot carrier injection to the floating gate 111.
Meanwhile, an erasing operation of the conventional split-gate flash memory is as follows. As shown in FIG. 4B, a high voltage VDD is applied to the word line 116, and a low voltage OV is applied to the source and drain junction regions 107 and 119, so that electrons accumulated in the floating gate 111 causes Fowler-Nordheim (F-N) tunneling to the word line 116 and thus are erased from the floating gate 111.
However, the conventional split-gate flash memory has problems in that the resistance of the word line 116 can increase and in that a short circuit may occur between the word line 116 and the drain junction region 119. This is explained in detail with reference to FIGS. 5A to 5D.
First, as shown in FIG. 5A, when the third conductive layer made of polycrystalline silicon is deposited and patterned, the third conductive layer can become over-etched, and therefore the resulting word line 116a is not completely formed, whereby the height of the word line 116a is lower than expected. As a result, the cross-sectional area of the word line 116a is relatively smaller and, therefore, the resistance of the word line is increased.
Also, as the height of the word line 116a is lowered, when a nitride layer 118a is later deposited and etched back as shown in FIG. 5B, a spacer 118b is formed on a side surface of the word line 116a, and portions of leftover nitride 130 are remain on the word line 116a as well, as shown in FIG. 5C. In addition, the spacer 118b formed on the side surface of the word line 116a becomes relatively smaller in area.
Therefore, as shown in FIG. 5D, when the silicide layers 120 are formed on the word line 116a and the drain junction region 119 through the silicidation process, since the nitride spacer 118b cannot sufficiently insulate the word line 116a and the drain junction region 119, a short circuit between the word line 116a and the drain junction region 119 may occur.
In addition, due to the portions of leftover nitride 130 remaining on the word line 116a, the area of the silicide layer 120 formed on the word line 116a becomes reduced, and, consequently, the resistance of the word line 116a becomes increased.
To overcome the limitations described above, it is an object of the present invention to provide a split-gate flash memory in which the word line resistance is relatively small.
It is another object of the present invention to provide a split-gate flash memory in which a short circuit between a drain junction region and a word line is mitigated or eliminated.
In order to achieve the above object, the preferred embodiments of the present invention provide a split-gate flash memory. The split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and having an outer side wall; a first junction region formed on a predertermined portion of the semiconductor substrate between two adjacent floating gates and having a reverse conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulator formed over the whole surface of the semiconductor and having a contact hole, the contact hole formed on a portion of the second junction region; and a second conductive line formed on the interlayer insulator and contacting the second junction region through the contact hole.
In another aspect, the present invention provides a split-gate flash memory, comprising: a first gate insulating layer formed on a semiconductor susbtrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predertermined portion of the semiconductor substrate between two adjacent floating gates and having a reverse conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermiend portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, having a vertical side wall and overlapping an end portion of the first spacer; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulator formed over the whole surface of the semiconductor and having a contact hole, the contact hole formed on a portion of the second junction region; and a second conductive line formed on the interlayer insulator and contacting the second junction region through the contact hole.
In yet another aspect, the present invention provides a method of manufacturing a split-gate flash memory. The method includes forming an array substrate including: a) a first gate insulating layer formed on a semiconductor susbtrate; b) a floating gate formed on the first gate insulating layer; c) a first spacer surrounding the floating gate and a side wall; d) a first junction region formed on a predertermined portion of the semiconductor substrate between two adjacent floating gates and having a reverse conductivity to that of the semiconductor substrate; and e) a first conductive line formed on the first junction region between the two adjacent first spacers; depositing sequentially a first insulating layer, a first conductive layer and a second insulating layer over the whole surface of the semiconductor substrate; etching the first conductive layer and the second insulating layer to a predetermined thickness to expose the first conductive line, a portion of the first conductive layer; forming a third insulating layer on the exposed conductive line and the exposed portion of the first conductive layer; removing the second insulating layer to expose a portion of the first conductive layer under the second insulating layer; etching simultaneously the first insulating layer and the first conductive layer using the second insulating layer as a mask to form a second gate insulating layer and a word line, the word line having a vertical side wall; forming a second spacer on the vertical wall of the word line; ion-implanting impurities having the same conductivity as the first junction region into the exposed portion of the semiconductor substrate to form a second junction region, the second junction region overlapping the second spacer; forming an interlayer insulating layer over the whole surface of the semiconductor substrate, the interlayer insulating layer having a contact holeformed on a portion of the second junction region; and forming a second condutive line on the interlayer insulator, the second conductive line contacting the second junction region through the contact hole.
In another embodiment, the present invention provides a method of manufacturing a split-gate flash memory. The method includes forming an array substrate including: a) a first gate insulating layer formed on a semiconductor substrate; b) a floating gate formed on the first gate insulating layer; c) a first spacer surrounding the floating gate and having a side wall; d) a first junction region formed on a predertermined portion of the semiconductor substrate between two adjacent floating gates and having a reverse conductivity to the semiconductor substrate; and e) a first conductive line formed on the first junction region between two adjacent first spacers; forming sequentially a first insulating layer, a first conductive layer and a second insulating layer over the whole surface of the semiconductor substrate; etching the second insulating layer and the first conductive layer in a predetermined thickness to expose a portion of the first conductive layer; forming a third insulating layer on the exposed portion of the first conductive layer; removing the remaining second insulating layer to expose a portion of the first conductive layer under the remaining second insulating layer; etching the first conductive layer and the first insulating layer using the third insulating layer as a mask; removing the third insulating layer; patterning the first conductive layer and the first insulating layer to form a word line and a second gate insulating layer, the word line having a vertical side wall; forming a second spacer on the vertical side wall; ion-implanting impurities having the same conductivity as the first conductive line into the exposed portion of the semiconductor substrate to form a second junction region, the scond junction region overlapping the second spacer; forming an interlayer insulator over the whole surface of the semiconductor substrate, the interlayer insulating layer having a contact holeformed on a portion of the second junction region; and forming a second condutive line on the interlayer insulator, the second conductive line contacting the second junction region through the contact hole.
The split-gate flash memory according to the preferred embodiments of the present invention offers a number of advantages. Since the word line includes the vertical side wall and has a uniform width, increase in resistance of the word line due to area size reduction of the word line is prevented. Also, since the nitride spacer is formed only on a side wall of the word line, the nitride layer does not remain on the word line. Moreover, a short circuit between the drain junction region and the word line is prevented due to the nitride spacer.